1. Field of the Invention
The present invention generally relates to load generating apparatuses and load testing methods, and more particularly to a load generating apparatus which has address controlling and data generating functions and applies a load on a bus of a test target system, and to a load testing method that uses such a load generating apparatus.
2. Description of the Related Art
FIGS. 1A and 1B are diagrams for explaining conventional load generating environments that apply a large load on a test target system, such as a personal computer and a server. In FIGS. 1A and 1B, a test target system 500 has a CPU 501, a system controller 502, an input and output (I/O) controller 503, and a memory 504.
In the case of a load generating environment A shown in FIG. 1A, a large number of hard disks 511 and a plurality of disk controllers 512 are required because there are a plurality of transmitting addresses for the data patterns and data. On the other hand, in the case of a load generating environment B shown in FIG. 1B, the generation of the test pattern, including the generation of data patterns, is committed to a plurality of external apparatuses such as personal computers (PCs) 521, and each load generating apparatus 522 in the load generating environment B only has a role of an interface with respect to the test target system 500 which executes only the external test patterns. In addition, since the test target system 500 and the PCs 521 that generate the test pattern are separated in the load generating environment B, a complex control, such as synchronizing the test target system 500 and the PCs 521 and controlling the load generating timing, becomes necessary in order to improve the load efficiency in the case of a long-term test.
FIG. 2 is a diagram for explaining generation of the load in the load generating environments A and B. As shown in FIG. 2, with respect to each of address spaces 531 through 534 of the memory 504 which becomes a main memory, for example, a load target address (that is, an access target address) is determined for each disk controller 512 or for each load generating apparatus 522. In the load generating environment A, it is possible to make a single disk controller operate similarly to the plurality of disk controllers 512, but this requires complex control by software, and the load applied to the test target system 500 does not become large due to the software intervention. In the load generating environment B, the test patterns should be changed for the address space 531→the address space 532→the address space 533→the address space 534, but since the test patterns are generated by the PCs 521, the load generating apparatus 522 does not have the function of generating such test patterns.
As a technique that is often used to increase the efficiency with which the load is applied to the test target system 500, there is a conventional load testing method that applies the load for each of the WAYs of the CPU 501. If it is assumed that the address spaces 531 through 534 shown in FIG. 2 are cache regions of each of the WAYs of the CPU 501, this conventional load testing method requires a number of disk controllers 512 corresponding to the number of WAYs or, a number of load generating apparatuses 522 corresponding to the number of WAYs. In addition, the structure of the disk controllers 512 or the load generating apparatus 522 becomes different if the number of WAYs of the cache becomes different depending on the structure of the test target system 500.
Therefore, according to the conventional load testing method, large-scale hardware resources are required because of the need to prepare load data patterns using extended storages such as the hard disks 511 and the extended memories (not shown) of the PCs 521. In addition, in both the load generating environments A and B, a complex control by software is required or, an extremely large amount of test patterns is required. As a result, it is not easy to build a testing (or inspecting) system for carrying out the load test on the test target system, and it is also difficult to easily carry out the debugging.
The applicant is aware of the background art described in Japanese Laid-Open Patent Applications No. 8-313602 and No. 10-312311.
Accordingly, in the conventional load testing method, there were problems in that it is difficult to efficiently apply a large load on the test target system, and that large-scale hardware resources are required, due to the complex software control.